An example of the conventional digital phase shifting apparatus which is capable of shifting the phase of digital data by a fine step shorter than the sampling period of an A/D converter is disclosed in Japanese Patent Laid-open No. 63-222745. A block diagram showing the configuration of an ultrasonic diagnosing apparatus disclosed in Japanese Patent Laid-open No. 63-222745 is shown in FIG. 7.
In this ultrasonic diagnosing apparatus 51, a signal received from a probe 2 undergoes phase adjustment for all channels by a number of delay circuits (or phase shifting circuits): a first-channel delay circuit 81 to an nth-channel delay circuit 8n. The outputs of the delay circuits are then summed up by an adder 5. The adder 5 carries out a beam forming process for generating a sound-ray reception signal. Based on all the sound-ray reception signals, a scan converter 6 produces pictures to be displayed on a display apparatus 7.
A detailed block diagram of the first-channel delay circuit 81 is shown in FIG. 8. The delay circuits of the other channels each have entirely the same configuration. A signal received by the first-channel delay circuit 81 is supplied to an A/D converter 82. A clock signal having a predetermined period .DELTA.T is fed to a sampling signal delay means 83. A synchronization signal also having the predetermined period .DELTA.T is supplied to a synchronization means 84. The synchronization means 83 delays the clock signal by a time .tau.1 shorter than the period .DELTA.T, producing a sampling signal output to the A/D converter 82.
The A/D converter 82 samples the signal received by the first-channel delay circuit 81 at sampling intervals equal to .DELTA.T by using the sampling signal, converting the received signal into digital data. The signal received by the first-channel delay circuit 81 is denoted by notations D and D' in FIGS. 9 and 10 respectively. Digital data obtained by using sampling signals with delay times different from each other is, on the other hand, denoted by symbols and .smallcircle. in FIGS. 9 and 10 respectively. For a sampling interval .DELTA.T of 100 ns, the symbols and .smallcircle. denote sampled digital data for .tau.1 equal to 0 and 50 ns respectively.
The synchronization means 84 is used for synchronization. For example, a train of sampled digital data denoted by the symbol .smallcircle. lags behind a train of sampled digital data due to the synchronization by .tau.1, which is shorter than the sampling period, as shown in FIG. 11. A digital delay means 85 is used for further delaying a signal output by the synchronization means 84 by a delay time T1 which is equal to a multiple of the sampling interval .DELTA.T. As a result, the first-channel delay circuit 81 outputs digital data lagging behind the signal received by the first channel by (.tau.1+T1).
A case with T1 and .tau.1 having values of 200 ns and 50 ns respectively is shown in FIG. 12. As a whole, the train of sampled digital data denoted by the symbol .smallcircle. lags behind the train of sampled digital data denoted by the symbol by a total of 250 ns.
In the conventional delay circuits 81 to 8n described above, however, sampling signals to shift the phase by amounts of time slightly different from channel to channel must inevitably be used, giving rise to a problem that the control becomes complicated.